Conventionally, a Dynamic Random Access Memory (DRAM) has been used as a semiconductor storage device. Recently, a Double Data Rate (DDR) method is employed as a fast data transfer method in order to address high speed system operation. A DRAM using DDR is called as a Double Data Rate Synchronous DRAM (DDR-SDRAM) or a DDR2-SDRAM.
The Double Data Rate SDRAM (hereinafter, simply referred to as a “memory”) outputs data in synchronization with a data strobe signal. A memory controller, included in a system circuit that is coupled to the memory, accesses the memory in response to a request from a CPU included in the system circuit. As illustrated in FIG. 1, the memory controller includes a Delay Locked Loop (DLL) circuit 101 and flip-flop circuits 102 and 103. As illustrated in FIG. 2, the DLL circuit 101 generates a delayed data strobe signal (hereinafter, referred to as a “delay signal”) DQSd that is delayed for a given time from the data strobe signal DQS. The flip-flop circuit 102 latches the data DQ in response to the delay signal DQSd. The flip-flop circuit 103 latches an output signal of the flip-flop circuit 102 in response to a clock signal (not illustrated) of the system side. The output signal of the flip-flop circuit 103 is used as read data (RD) of the system circuit.
The DLL circuit 101 generates a second delay signal (not illustrated in FIG. 1) with a phase that differs from the phase of the delay signal DQSd by 180 degree. The memory controller includes a flip-flop circuit for latching the data DQ by the second delayed strobe signal. The flip-flop circuit and the above described flip-flop circuits 102 and 103 receive data that is output substantially in synchronization with a rising edge and a falling edge of the data strobe signal DQS.
According to the above described configuration, the system circuit receives an input signal, such as the data DQ, substantially in synchronization with a rising edge and a falling edge of the data strobe signal DQS. The memory outputs the data DQ substantially in synchronization with the data strobe signal DQS. The flip-flop circuit 102 receives the data DQ by setting a delay time of the DLL circuit 101 to a ¼ (90 degree out of phase) of the data strobe signal DQS, and thereby adjusting a timing to receive the data DQ by the delay signal DQSd to a center of a period during which the data DQ is valid (a pulse center).
A delay time of a wiring for each circuit (each chip) may vary with variations in forming a system circuit. In this case, an arrival time of the delay signal DQSd and an arrival time of the data DQ to the flip-flop circuit 102 differ. In other words, an edge timing of the delay signal DQSd deviates from the center of the period in which the data DQ is valid. The differences of the timings of the data DQ and the delay signal DQSd makes the flip-flop circuits 102 and 103 latch wrong data. This may cause an error in the read data RD because the period in which the data DQ is valid is short in a system circuit with a high transfer speed.
Thus, some circuits included in a system circuit may perform a training operation (timing calibration) for adjusting a delay time by changing a delay time of the DLL circuit 101 at an activation and repeating operation to read data with a given value (for example, see Japanese Laid-open Patent Publication No. 2003-91453).
A relative difference of timing between the data DQ and the delay signal DQSd may also be caused by a change in environmental temperature of the system circuit and a change of an operation power supply voltage of the system circuit. The differences of timings cause an error in the read data RD. Executing a training operation again causes an overhead for read and write operation in the system circuit that accesses the memory.